The present invention relates to a computer input/output (I/O) interface and more particularly to a virtual I/O device coupled to a microprocessor through a memory controller of the computer.
Conventionally, a microprocessor of a computer acts to perform two major tasks (e.g., data I/O and data processing) and others. In many cases data I/O is more frequently executed as compared with data processing (which occurs only occasionally). While an operating system (OS) of the computer plays a role in managing and controlling a data I/O interface and I/O device with respect to data input and output. Most importantly, the OS is operative to couple to a plurality of peripherals such as printers, scanner, card readers, camcorders, hubs, digital cameras, etc. referring to FIG. 1, constituent components of a typical microprocessor 10 of a computer plays comprise three major parts in terms of tasks being performed. The three major parts are an arithmetic and logic unit (ALU) 11 for performing arithmetic operations, logical operations, and all other operations associated with the arithmetic operations; a memory controller 12 coupled to the ALU 11 through a data bus, a control bus, and an address bus and coupled to a memory unit 20 through the data bus and the address bus so that the memory controller 12 can be controlled by the ALU 11 for reading programs and data from the memory unit 20 through the data bus and the address bus or writing intermediate data and results generated in the operations into the memory unit 20; and an I/O interface 13 coupled to the ALU 11 through the data bus, the control bus, and the address bus and coupled to an I/O device 30 through the data bus and the address bus so that the I/O interface 13 can be controlled by the ALU 11 for outputting data to the I/O device 30 or receiving data sent back from the I/O device 30. Hence, the microprocessor 10 of the computer can be coupled to the plurality of peripherals (e.g., printers, scanners, card readers, mouses, etc.) for controlling the same in order to achieve assigned tasks.
In the typical microprocessor 10 as stated above, the I/O interface 13 is operative to communicate instructions and data packets with the I/O device 30 by means of a complete protocol. Also, basically a handshake including a request and an acknowledgement is performed during a transmission or receiving of the packets. That is, when the microprocessor 10 desires to perform an instruction (e.g., reading, writing, continuous reading, continuous writing, DMA (direct memory access) conversion, interrupt signal, or status report), the microprocessor 10 may generate an associated setup token and data for forming a request packet. The packet is then sent to the I/O interface 13. Next, the I/O interface 13 processes the received packet prior to transmission to the I/O device 30. In the I/O device 30 a parsing is performed on the packet. Once instructions contained in the request packet are acknowledged, an acknowledgement packet will be generated for sending back to the I/O interface 13. This completes the handshake. Also, the parsed instructions are sent to a peripheral coupled to the I/O device 30. In response to a receiving of the packet, the peripheral is commanded by the microprocessor 10 to perform an assigned task. As to interrupt signal sent from the peripheral, the interrupt signal is again sent to the ALU 11 via the I/O device 30. Next, the ALU 11 stores the received interrupt signal in a packet being sent or received in a queue. Further queuing and storing procedures are performed for completion after the interrupt signal stopped.
A block diagram schematically depicting a packet transmission and receiving between the I/O interface 13 of the typical microprocessor of computer and the typical I/O device 30 is shown in FIG. 2. The I/O interface 13 generally comprises a plurality of frequently installed interface specifications for bus such as an AGP (Accelerated Graphics Port) 131, a PCI (Peripheral Component Interconnect) 132, an ISA (Industry Standard Architecture) 133, and a USB (Universal Serial Bus) 134. As such, the I/O interface 13 can process data in accordance with one of the various interface specifications for bus when the I/O interface 13 acts to send data between the microprocessor 10 and the peripherals. As to the interface specifications for bus, the AGP 131 is developed by Intel Corporation for 3D graphics having a very high data transmission capability. In detail, the AGP 131 is the most widely used bus for display card. The AGP 131 has a channel of 32 bits, a frequency of 66 MHz, and a maximum transmission rate of 1,056 MB. Further, the AGP bus does access data from memory directly rather than via the PCI bus. The PCI 132 is developed by Intel Corporation also as a bus for personal computer. The PCI 132 acts to enable respective peripherals to directly access a CPU (Central Processing Unit) of computer for increasing a data transmission rate between the microprocessor and the coupled peripheral. In detail, the PCI has a channel of 32 bits, a frequency of 66 MHz, and a maximum transmission rate of 264 (equal to 33xc3x978) MB. Currently, the PCI has become a standard for Pentium, PowerPC and 486 bus. As to the ISA 133, it is a bus for personal computer. The ISA 133 has a data transmission rate of 16.66 BM. The ISA card is network interface card of 16 bits. A slot having a length about 13 cm to 14 cm provided on a motherboard of computer is reserved for ISA card. As to USB 134, it is a bus for interconnecting the computer and any coupled peripheral. The USB 134 is a data transmission standard being jointly developed by a number of global information companies such as Intel, IBM, Microsoft, Compaq, Northern Telecom, and Dell. The USB can perform either a full-speed data transmission mode of 12 Mbps or a lower-speed data transmission mode of 1.5 Mbps. Also, any peripheral incorporating the USB as data transmission interface has Plug-and-Play and hot insertion capabilities.
Referring to FIG. 2 again, the I/O device 30 comprises a plurality of converters 301, 302, 303, and 304 for cooperating with the embedded interface specifications for bus. Further, the converters 301, 302, 303, and 304 can parse a packet sent from one of the various interface specifications for bus. Furthermore, an acknowledgement packet is generated to send to the I/O interface 13 as instructions contained in the packet are acknowledged. This completes the handshake. At the same time, the parsed instructions are sent to the peripheral having corresponding interface specifications for bus, the peripheral being coupled to the I/O device 30. In response to a receiving of the packet, the peripheral is commanded by the instructions sent from the microprocessor to perform an assigned task.
In view of the above, an excessive time is spent on processing of a request and acknowledge in a handshake as a packet receiving or transmission between the I/O interface 13 and the I/O device 30 is performed. Also, the converters 301, 302, 303, and 304 in the I/O device 30 can only parse a packet with respect to the corresponding interface specifications for bust that are embedded in the I/O interface 13. As a result, the performance of the computer cannot increase correspondingly. Also, compatibility of the interface specifications for bus in the microprocessor is poor because it is limited by the corresponding converters in the I/O device 30. Thus a need for improvement exists.
The invention relates to a virtual I/O device coupled to a memory controller in a microprocessor of a computer, the virtual I/O device and a memory unit being in communication with the memory controller via a common interface so that a plurality of peripherals is capable of coupling to an arithmetic and logic unit (ALU) in the microprocessor via the virtual I/O device and the memory controller sequentially. The ALU is capable of writing an instruction packet into the virtual I/O device via the memory controller as any peripheral is commanded by the ALU, the virtual I/O device sending the written instruction packet to the peripheral, and the peripheral being commanded to perform an assigned task in response to receiving of the instruction packet; or alternatively, in response to receiving of a response packet from any peripheral, the virtual 110 device commanding the ALU to read the received response packet from the virtual I/O device via the memo controller.
A primary object of the present invention is to provide the virtual I/O device as a replacement for the conventional I/O device so that an excessive time spent on processing a request and acknowledgment in a handshake as packet receiving or transmission between the conventional I/O device and the I/O interface in the microprocessor is being performed is significantly reduced to a value of about zero, resulting in a great improvement of the computer performance.
Another object of the present invention is to enable the virtual converter to parse and compile the packet in accordance with one of the various interface specifications for bus so that a compatibility of the various interface specifications for bus in the microprocessor is not limited by the corresponding converters in the conventional I/O device, resulting in a greater flexibility.
The above and other objects, features and advantages of the present invention will become apparent from the following detailed description taken with the accompanying drawings.